BLOCK DIAGRAM
Description of Block Diagram:
The above block diagram shows the complete design of the processor. It consists of an 8-bit ALU which is used to perform all the arithmetic and logical instructions. Four 8-bit general purpose working registers namely A (Accumulator) and registers B, C and D are used to store the results. The program status word (PSW) presently consists of two flags: Carry flag and Zero flag. Only these two flags are needed according to the current design of the processor. The PSW can be expanded later on to include Parity flag, Auxiliary flag and others when designing new instructions. The instructions to the processor are fed through the instruction register which is a 16-bit register via the 16 bit input bus to the processor. The main function of the instruction decoder is to separate the different fields from the 16-bit number received from the instruction register .The instruction decoder decodes the instructions and provides the required data to each of the blocks. It generates the required control signals to execute a particular instruction and provides the data accordingly to the registers and the ALU.
The design consists of four 8-bit general purpose input/output ports namely A, B, C and D. Each port consists of a port register which is used to send data to the port or receive data from the port. The blocks are connected via the system buses. A 16 bit input bus to the system provides the instruction and the data to the processor. Timing and control unit generates the required control signals for execution of instructions.
INSTRUCTION EXECUTION AND INSTRUCTION DECODER FORMAT:
As stated in the abstract earlier that the design does not conists of the bus interface unit which is generally required for fetching the instructions and data from the external memory. The instruction are provided using a DIP switch and executed when switch pb1 is pressed. So, in this section we describe what happens when this switch is pressed. The instruction register is provided with the instruction as soon as the switch is pressed. The instruction register passes o this instruction to the instruction decoder. The instruction decoder the separates the fields from the 16-bit number provided to it. It then provides the different blocks with different data fron this 16-bit number. Let us consider an example at this place. Suppose the instruction fed to the processor is
ADD A,#22H. Which is add immediate data 22(Hex) to the Accumulator register and store the result in Accumulator itself. The format of instruction decode is as shown below. The bits 15 to 13 indicate the opcode that is the instruction. Bit 12 indicates the addressing mode. Addressing mode refers to the style in which the data is provided to the processor. Bits 11-8 indicate the destination. And bit 7-0 indicates the source of the data. Thus as the instruction is put into the instruction decoder the fields are separated and the processor know what operation is to be performed, what is the addressing mode, what is the destination of the result(port or register) and what is the source of the data. In our example (the add instruction) the addressing mode is immediate so the data is present in the instruction and is the last 8 bits (LSB) of the instruction. Also the destination is Accumulator. It should also be noted that the operation is to be performed on Accumulator so one of the data is present in the Accumulator to which the immediate data is to be added. Now the processor clearly knows what it has to do to get the results. As ADD is an arithmetic instruction the processor needs to use ALU for executing this instruction. Before we analyze the flow of the instruction let us summarize the complete information provided to the processor by the instruction.
Bits 15-13 => Instruction <=
Bit 12 =>’1’ Addressing Mode =>Immediate
Bits 11-8 => Destination <= Accumulator
Bits 7-0 => Data (As addressing mode is immediate)
| Bits 15-13 | Bit 12 | Bits 11-8 | Bits 7-0 |
OPCODE ADDRESSING DESTINATION SOURCE MODE
VHDL Code
The simulation results obtained by Simulating the Code on ModelSim 6.3 are shown below:
FIG.1 Instruction Register
FIG.2 ALU
FIG.3 Synchro. Unit
